1. Field of the Invention
The present invention relates to electrically erasable and programmable memories integrated onto silicon chips, and more particularly to programming memory cells in such memories.
2. Description of the Related Art
Electrically erasable and programmable memories, particularly Flash memories, are generally designed to execute a programming operation in several cycles. Each cycle comprises, for each memory cell that is to be programmed, a step of verifying the state of the memory cell and a step of programming the memory cell. The programming step is performed if the memory cell is seen as not being in the programmed state during the verify step.
An example implementation of the verification step is shown in FIG. 1A. FIG. 1A represents a Flash-type memory cell formed by an NMOS-type floating-gate transistor CFGT. The memory cell is arranged in a memory array (not represented) comprising a plurality of memory cells arranged in lines and columns, such that the drain D of the transistor CFGT is linked to a bit line BL, its source S is linked to a source line SL, and its control gate G is linked to a word line WL. The verify step is performed by a sense amplifier SA linked to the bit line BL. The sense amplifier SA applies a determined drain-source voltage to the transistor CFGT, generally a voltage on the order of 1V, while a read voltage Vy1 is applied to the control gate G. The amplifier SA compares the drain-source current Ids flowing through the transistor with a reference current Iref1. If the current Ids is lower than Iref1, the memory cell is considered to be in a programmed state. If the current Ids is greater than Iref1, the memory cell is considered to be in an erased state.
The voltage Vy1 is greater than a reference voltage VTref that represents the minimum threshold voltage targeted for a floating-gate transistor to be considered to be in the programmed state. The reference current Iref1 corresponds to the current flowing through a floating-gate transistor having the threshold voltage VTref, when the latter receives the voltage Vy1 at its control gate.
An example of implementation of the programming step is shown in FIG. 1B. A pulse of a programming voltage Vpp, generally on the order of 5 to 10V, is applied between the drain and the source of the transistor CFGT, while a voltage Vgp is applied to its control gate. A current passes through the channel of the transistor CFGT and negative electric charges are injected and trapped in the floating gate (FG) of the transistor. The threshold voltage VT of the transistor increases by a determined increment. After one or more programming voltage Vpp pulses, each preceded by a verify step, the threshold voltage VT of the transistor reaches, in principle, a value at least equal to the reference voltage VTref.
Thus, the statistical distribution of the threshold voltages of a plurality of memory cells within a same memory array must, in principle, conform to a curve DS1 represented in FIG. 2, and the threshold voltages must be between the reference voltage VTref, on the order of 6V for example, and a maximum voltage VTmax, on the order of 9V for example, the voltage Vy1 being on the order of 6.5V for example. FIG. 2 further represents a curve DS2 showing the statistical distribution of the threshold voltages of memory cells in the erased state, which is between 0.5V and 2.5V for example. A read voltage Vread, representing the gate voltage applied to the memory cells during a normal read of the memory array, is also represented. The voltage Vread is different from the read-verify voltage Vy1 and is between the two distribution curves DS1, DS2, for example in the vicinity of 4.5V.